AFE4403 datasheet(22/97 Pages) TI

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ADC

VTIA+

VTIA-

CIN

Iin

Sensor Model

AFE4403

SBAS650B – MAY 2014 – REVISED JULY 2014

www.ti.com

Feature Description (continued)

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component

resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a

current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the

pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and

12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-

bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value

can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the

dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage

allows for more of the available ADC dynamic range to be used.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,

the amplifier output is filtered and sampled on capacitor CLED2. Similarly, the LED1 signal is sampled on the

CLED1 capacitor when LED1 is on. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to

estimate the ambient signal on capacitors CLED2_amb and CLED1_amb.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The

sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx

sample time is used for all dynamic range calculations; the minimum time recommended is 50 µs. While the

AFE4403 can support pulse widths lower than 50 us, having too low a pulse width could result in a degraded

signal and noise from the photodiode.

A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion

provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions

are meant to be staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so

on.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at

the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that

additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

The model of the photodiode and the connection to the TIA is shown in Figure 37.

Figure 37. TIA Block Diagram

Iin is the signal current generated by the photodiode in response to the incident light. Cin is the zero-bias

capacitance of the photodiode. The current-to-voltage gain in the TIA is given by Equation 2:

VTIA (diff) = VTIA

+ – V

TIA

– = 2 × I

in × RF

(2)

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