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AFE4403 Datasheet(PDF) 11 Page - Texas Instruments |
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AFE4403 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 97 page ![]() }v[, can be high or low. A7 A6 A1 A0 SPISTE SPISIMO SCLK D22 D17 D16 D6 D1 SPISOMI XIN tCLK tSTECLK tSPICLK tSOMIPD tSOMIHD tCLKSTEL tCLKSTEH tSIMOSU tSIMOHD 31 D23 tSOMIPD D7 0 7 D0 23 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 7.6 Timing Requirements PARAMETER MIN TYP MAX UNIT tCLK Clock frequency on the XIN pin 8 MHz tSCLK Serial shift clock period 62.5 ns tSTECLK STE low to SCLK rising edge, setup time 10 ns tCLKSTEH,L SCLK transition to SPI STE high or low 10 ns tSIMOSU SIMO data to SCLK rising edge, setup time 10 ns tSIMOHD Valid SIMO data after SCLK rising edge, hold time 10 ns tSOMIPD SCLK falling edge to valid SOMI, setup time 17 ns tSOMIHD SCLK rising edge to invalid data, hold time 0.5 tSCLK (1) The SPI_READ register bit must be enabled before attempting a register read. (2) Specify the register address whose contents must be read back on A[7:0]. (3) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 1. Serial Interface Timing Diagram, Read Operation(1)(2)(3) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: AFE4403 |
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