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AFE4403 Datasheet(PDF) 49 Page - Texas Instruments |
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AFE4403 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 97 page ![]() Pulse repetition period Sample LED2 Sample LED1 Sample Ambient 2 Sample Ambient 1 Convert LED2 Convert LED1 Convert Ambient 2 Convert Ambient 1 PDN_CYCLE t1 t2 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.4.1.3 Dynamic Power-Down Mode When operated at low PRF, a dynamic power-down mode can be optionally enabled to shut off blocks during a portion of each period. This operation is illustrated in Figure 67. The dynamic power-down signal (called PDN_CYCLE) can be internally generated using the timing controller. PDN_CYCLE can be used to shut off power to internal blocks during the unused section within each pulse repetition period. Figure 67. Dynamic Power-Down Mode Timing t1 and t2 denote the timing margin between the active portion of the period and the dynamic power-down signal. TI recommends setting t1 > 50 µs and t2 > 200 µs in order to ensure sufficient time for the shutdown blocks to recover from power-down. By choosing the blocks that are shut down during dynamic power-down, a power savings of anywhere between 35% to 70% power can be achieved when the PDN_CYCLE phase is active. The sequence of the convert phases within a pulse repetition period should be as follows: LED2 (Red) → Ambient 2 → LED1 (IR) → Ambient 1. The sample phases must precede the corresponding convert phase. Also note that the ADC_RDY signal comes at the beginning of the pulse repetition period. Thus, the contents of the registers must be read before the completion of the first conversion phase in the pulse repetition period. These contents correspond to the samples of the four phases from the previous pulse repetition period. The DYNAMIC1, DYNAMIC2, DYNAMIC3, and DYNAMIC4 bits determine which blocks are powered down during the dynamic power-down state (when PDN_CYCLE is high). For maximum power saving, all four bits can be set to 1. TI recommends setting t1 to greater than 100 µs and t2 to greater than 200 µs to ensure that the blocks recover from power-down in time for the next cycle. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: AFE4403 |
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