AFE4403 datasheet(9/97 Pages) TI

9 / 97 page

AFE4403

www.ti.com

SBAS650B – MAY 2014 – REVISED JULY 2014

Electrical Characteristics (continued)

Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled,

detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V,

and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2

amplifier disabled, and fCLK = 8 MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL CLOCK

For SPO2 applications

Maximum allowable external clock jitter

For optical heart rate only

1000

External clock input frequency (2)

±2%

MHz

0.75 ×

Voltage input high (VIH)

RX_DIG_SUP

External clock input voltage

0.25 ×

Voltage input low (VIL)

RX_DIG_SUP

TIMING

Wake-up time from complete

1000

power-down

Wake-up time from Rx power-down

100

µs

Wake-up time from Tx power-down

1000

tRESET

Active low RESET pulse duration

DIAG_END pulse duration at the

CLKOUT

tDIAGEND

completion of diagnostics

cycles

CLKOUT

tADCRDY

ADC_RDY pulse duration

cycle

DIGITAL SIGNAL CHARACTERISTICS

0.8

DVDD +

VIH

Logic high input voltage

AFE_PDN, SCLK, SPISIMO, SPISTE, RESET

> 1.3

DVDD

0.1

0.2

VIL

Logic low input voltage

AFE_PDN, SCLK, SPISIMO, SPISTE, RESET

–0.1

< 0.4

DVDD

IIN

Logic input current

0 V < VDigitalInput < DVDD

–10

µA

0.9

> (RX_DIG_SUP –

VOH

Logic high output voltage

DIAG_END, SPISOMI, ADC_RDY, CLKOUT

DVDD

0.2 V)

0.1

VOL

Logic low output voltage

DIAG_END, SPISOMI, ADC_RDY, CLKOUT

< 0.4

DVDD

SUPPLY CURRENT

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

0.6

Rx stage 2 disabled

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

Receiver analog supply current

0.7

Rx stage 2 enabled

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

0.49

Rx stage 2 disabled, external clock mode

Receiver digital supply current

RX_DIG_SUP = 3.0 V

0.15

LED driver supply current

With zero LED current setting

µA

Transmitter control supply current

µA

Receiver current only (RX_ANA_SUP)

µA

Receiver current only (RX_DIG_SUP)

µA

Complete power-down

(using the AFE_PDN pin)

Transmitter current only (LED_DRV_SUP)

µA

Transmitter current only (TX_CTRL_SUP)

µA

Receiver current only (RX_ANA_SUP)

200

µA

Power-down Rx alone

Receiver current only (RX_DIG_SUP)

150

µA

Transmitter current only (LED_DRV_SUP)

µA

Power-down Tx alone

Transmitter current only (TX_CTRL_SUP)

µA

(2)

Refer to the CLKDIV[2:0] register bits for a detailed list of input clock frequencies that are supported.

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