DLPC900 datasheet(18/72 Pages) TI1

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DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

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Power and Ground Pin Functions (continued)

I/O TYPE

DESCRIPTION

NAME

NUMBER

1.15-V video-2X clock generator PLL

PLLS_VAS

R24

GND

Analog GND

B18, D18, B17, E17, A18, C18, A17,

L_VDQPAD_[7:0],

D17, AE17, AC17, AF17, AC18, AB16,

DRAM direct test pins (for manufacturing use only). These

RES

R_VDQPAD_[7:0]

AD17,

pins should be tied directly to ground for normal operation.

AB17, AD18

DRAM direct test control pin (for manufacturing use only).

CFO_VDD33

AE26

RES

This pin should be tied directly to 3.3 I/O power (VDD33) for

normal operation.

DRAM direct test control pins (for manufacturing use only).

VTEST1, VTEST2,

AB14, AB15, E15, E16

RES

These pins should be tied directly to ground for normal

VTEST3, VTEST4

operation.

LVDS_AVS1,

Dedicated ground for LVDS bandgap reference. These pins

V5, K5

PWR

LVDS_AVS2

should be tied directly to ground for normal operation.

Fuse programming pin (for manufacturing use only). This

VPGM

AC6

PWR

pin should be tied directly to ground for normal operation.

A26, A25, A24, B25, C24, D23,

E22, F21, F18, F15, F12, F9, F6,

E5, D4, C3, B3, A3, B2, A2,

B1, A1, G5, J5, J6, L5, M6,

N5, R5, R6, U5, V6, W5, Y5,

AA6, AB5, AC4, AD3, AE3, AF3, AF2,

AF1, AA9, AA12, AA15, AA18, AA21,

GND

AB22,

GND

Common ground

AC23, AD24, AE24, AF24, AE25,

AF25, AF26,

V21, M21, J21, L15, L14, L13, L12,

M16, M15, M14, M13, M12, M11, N16,

N15, N14, N13, N12, N11, P16, P15,

P14, P13, P12, P11, R16, R15, R14,

R13, R12, R11, T15, T14, T13, T12

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