DLPC900 datasheet(11/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

Port 1 and Port 2 Channel Data and Control Pin Functions (continued)

PIN (1) (2) (3)

I/O

I/O TYPE

CLK SYSTEM

DESCRIPTION

POWER

NAME

NUMBER

P2_A9

AD26

Port 2 A channel input pixel data (bit weight 128)

P2_A8

AD25

Port 2 A channel input pixel data (bit weight 64)

P2_A7

AB21

Port 2 A channel input pixel data (bit weight 32)

P2_A6

AC22

Port 2 A channel input pixel data (bit weight 16)

P_CLK1,

P2_A5

AD23

Port 2 A channel input pixel data (bit weight 8)

VDD33

P_CLK2, or

P2_A4

AB20

Port 2 A channel input pixel data (bit weight 4)

P_CLK3

P2_A3

AC21

Port 2 A channel input pixel data (bit weight 2)

P2_A2

AD22

Port 2 A channel input pixel data (bit weight 1)

P2_A1 (1)

AE23

Unused, tie to 0

P2_A0 (1)

AB19

Unused, tie to 0

P2_B9

Y22

Port 2 B channel input pixel data (bit weight 128)

P2_B8

AB26

Port 2 B channel input pixel data (bit weight 64)

P2_B7

AA23

Port 2 B channel input pixel data (bit weight 32)

P2_B6

AB25

Port 2 B channel input pixel data (bit weight 16)

P_CLK1,

P2_B5

AA22

Port 2 B channel input pixel data (bit weight 8)

VDD33

P_CLK2, or

P2_B4

AB24

Port 2 B channel input pixel data (bit weight 4)

P_CLK3

P2_B3

AC26

Port 2 B channel input pixel data (bit weight 2)

P2_B2

AB23

Port 2 B channel input pixel data (bit weight 1)

P2_B1 (1)

AC25

Unused, tie to 0

P2_B0 (1)

AC24

Unused, tie to 0

P2_C9

W23

Port 2 C channel input pixel data (bit weight 128)

P2_C8

V22

Port 2 C channel input pixel data (bit weight 64)

P2_C7

Y26

Port 2 C channel input pixel data (bit weight 32)

P2_C6

Y25

Port 2 C channel input pixel data (bit weight 16)

P_CLK1,

P2_C5

Y24

Port 2 C channel input pixel data (bit weight 8)

VDD33

P_CLK2, or

P2_C4

Y23

Port 2 C channel input pixel data (bit weight 4)

P_CLK3

P2_C3

W22

Port 2 C channel input pixel data (bit weight 2)

P2_C2

AA26

Port 2 C channel input pixel data (bit weight 1)

P2_C1 (1)

AA25

Unused, tie to 0

P2_C0 (1)

AA24

Unused, tie to 0

P_CLK1,

Port 2 vertical sync. While intended to be associated with

P2_VSYNC

U22

VDD33

P_CLK2, or

port 2, it can be programmed for use with port 1.

P_CLK3

P_CLK1,

Port 2 horizontal sync. While intended to be associated with

P2_HSYNC

W26

VDD33

P_CLK2, or

port 2, it can be programmed for use with port 1.

P_CLK3

Clock and PLL Support Pin Functions

I/O

I/O TYPE

CLK SYSTEM

DESCRIPTION

POWER

NAME

NUMBER

System clock oscillator input (3.3-V LVTTL). MOSC must be

MOSC

M26

VDD33

I10

N/A

stable a maximum of 25 ms after POSENSE transitions from

low to high.

MOSCN

N26

VDD33

O10

N/A

MOSC crystal return.

General-purpose output clock A. The frequency is software

programmable. Power-up default is 787 kHz and the output

OCLKA (1)

AF6

VDD33

Async

frequency is maintained through all operations, except

power loss and reset.

(1)

This signal does not apply to the slave controller in a two controller system configuration. On the slave controller, this pin is reserved

and should be left unconnected. Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description

between a one controller and a two controller configuration.

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