DLPC900 datasheet(32/72 Pages) TI1

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DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

DADSTRB

tw(H)

todv-min

todv-max

50%

DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

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6.14 DMD Interface Switching Characteristics

(1)

over recommended operating conditions, CL (min timing) = 5 pF, CL (max timing) = 50 pF (unless otherwise noted)

PARAMETER

FROM

MIN

MAX

UNIT

DMD TIMING MODE 0 (2)

tw(H)

DMD strobe high pulse duration

N/A

DADSTRB

tw(L)

DMD strobe low pulse duration

N/A

DADSTRB

Output data valid window,

DADADDR_(3:0)

Todv-min

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

DADMODE_(1:0)

DADSTRB

↑(1)

–27

with respect to DADSTRB

DADSEL_(1:0)

Output data valid window,

DADADDR_(3:0)

Todv-max

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

DADMODE_(1:0)

DADSTRB

↑(1)

with respect to DADSTRB

DADSEL_(1:0)

DMD TIMING MODE 1 (2)

tw(H)

DMD strobe pulse duration

N/A

DADSTRB

tw(L)

DMD strobe low pulse duration

N/A

DADSTRB

Output data valid window,

DADADDR_(3:0)

Todv-min

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

DADMODE_(1:0)

DADSTRB

↑(1)

–12

with respect to DADSTRB

DADSEL_(1:0)

Output data valid window,

DADADDR_(3:0)

Todv-max

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

DADMODE_(1:0)

DADSTRB

↑(1)

with respect to DADSTRB

DADSEL_(1:0)

(1)

DMD control signals are captured on the rising edge of DADSTRB within the DMD.

(2)

The DMD timing mode is controlled by the controller firmware.

Figure 10. DMD Interface Timing

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