DLPC900 datasheet(55/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

Layout Guidelines (continued)

High-frequency decoupling is required for 1.15-V and 1.8-V PLL supplies and should be provided as close as

possible to each of the PLL supply package pins as shown in Figure 28. Placing decoupling capacitors under the

package on the opposite side of the board is recommended. High-quality, low-ESR, monolithic, surface-mount

capacitors should be used. Typically, 0.1 µF for each PLL supply should be sufficient. The length of a connecting

trace increases the parasitic inductance of the mounting, and thus, where possible, there should be no trace,

allowing the via to butt up against the land. Additionally, the connecting trace should be made as wide as

possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the

number of vias.

The location of bulk decoupling depends on the system design.

10.1.3 PCB Layout Guidelines for Quality Video Performance

One of the most important factors to gain good performance is designing the PCB with the highest quality signal

integrity possible. Here are a few recommendations:

1. Minimize the trace lengths between the video digital receiver and the DLPC900 port inputs.

2. Analog power should not be shared with the digital power directly.

3. Try to keep the trace lengths of the RGB as equal as possible.

4. Impedance matching between the digital receiver and the DLPC900 is important.

10.1.4 Recommended MOSC Crystal Oscillator Configuration

A recommended crystal oscillator configuration is shown in Figure 29.

It is assumed that the external crystal oscillator will stabilize within 50 ms after stable power is applied.

Table 13. Crystal Port Characteristics

PARAMETER

NOMINAL

UNIT

MOSC-to-GND capacitance

1.5

MOSCZ-to-GND capacitance

1.5

Table 14. Recommended Crystal Configuration (1)

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Parallel resonant

Crystal type

Fundamental (first harmonic)

Crystal nominal frequency

MHz

Crystal temperature stability

± 30

PPM

Crystal frequency tolerance (including accuracy,

± 100

PPM

temperature, aging, and trim sensitivity)

Crystal equivalent series resistance (ESR)

50 max

Crystal load

Crystal shunt load

7 max

RS drive resistor (nominal)

100

RFB feedback resistor (nominal)

CL1 external crystal load capacitor (MOSC)

See Equation 1

CL2 external crystal load capacitor (MOSCN)

See Equation 2

PCB layout

A ground isolation ring around the crystal is recommended

(1)

Typical drive level with the XSA020000FK1H-OCX crystal (ESRmax = 40 Ω) = 50 µW

CL1 = 2 × (CL – CStray-MOSC)

(1)

CL2 = 2 × (CL – CStray-MOSCN

(2)

where

•

CL = Crystal load capacitance (Farads)

•

CStray-MOSC = Sum of package and PCB capacitance at the crystal pin associated with controller signal MOSC.

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