DLPC900 datasheet(59/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

Table 15. General PCB Routing (Applies to All Corresponding PCB Signals refer to Figure 30) (continued)

PARAMETER

APPLICATION

SINGLE-ENDED

DIFFERENTIAL PAIRS

UNIT

SIGNALS

mil

Total data

N/A

(0.3)

(mm)

Maximum differential pair P-to-N length

mismatch

mil

Total clock

N/A

(0.3)

(mm)

Table 16. DMD Interface Specific PCB Routing

SIGNAL GROUP LENGTH MATCHING

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD

SCA_P/ SCA_N

± 150

mil

DCKA_P/ DCKA_N

(LVDS)

DDA_P_(15:0)/ DDA_N_(15:0)

(± 3.81)

(mm)

DMD

SCB_P/ SCB_N

± 150

mil

DCKB_P/ DCKB_N

(LVDS)

DDB_P_(15:0)/ DDB_N_(15:0)

(± 3.81)

(mm)

When routing the DMD Interface signals it is recommended to:

•

Minimize the number of layer changes for Single-ended signals.

•

Individual differential pairs can be routed on different layers but the signals of a given pair should not change

layers.

Table 17. DMD Signal Routing Length(1)

BUS

MIN

MAX

UNIT

DMD

375

(LVDS)

(1)

Max signal routing length includes escape routing.

Stubs: Stubs should be avoided.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100

internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements should be used:

•

Differential crosstalk: < 5%

•

Differential impedance: 75 to 125

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed

in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference

for each row should be accounted for on associated PCB etch lengths.

These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4

ps, assuming 175 ps/inch FR4 propagation delay.

These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold

margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.

Both the DLPC900 output timing parameters and the DMD input timing parameters include timing budget to

account for their respective internal package routing skew.

10.1.8.1 Flex Connector Plating

Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of

electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel.

10.1.9 PCB Design Standards

PCB designed and built in accordance with the following industry specifications:

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