DLPC900 datasheet(43/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

Typical Applications (continued)

Figure 21. Boot Flash Memory Layout

NOTE

The Bootloader, the Main Application, and any images stored in flash (if present) are

considered the firmware.

The chipset has the following interfaces and support circuitry:

•

DLPC900 System Interfaces

–

Control Interfaces

–

Trigger Interface

–

Input Data Interfaces

–

Illumination Interface

•

DLPC900 Support Circuitry and Interfaces

–

Reference Clock

–

PLL

–

Program Memory Flash Interface

•

DMD Interface

–

DLPC900 to DLP6500/DLP9000 Digital Data

–

DLPC900 to DLP6500/DLP9000 Control and Clock Interface

–

DLPC900 to DLP6500/DLP9000 Serial Communication Interface

8.2.1.2 Detailed Design Procedure

8.2.1.2.1

DLPC900 System Interfaces

The DLPC900 chipset supports a 24-bit parallel RGB interface for image data transfers from another device and

a 24-bit interface for video data transfers. The system input requires proper generation of the PWRGOOD and

POSENSE inputs to ensure reliable operation. There are two primary output interfaces: illumination driver control

interface and sync outputs.

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DLPC900 Datasheet(PDF) 43 Page - Texas Instruments

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