DLPC900 datasheet(12/72 Pages) TI1

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DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

www.ti.com

Board Level Test and Debug Pin Functions (1)

I/O

CLK

I/O TYPE

DESCRIPTION

POWER

SYSTEM

NAME

NUMBER

JTAG serial data in. Used in both Boundary Scan and ICE

TDI

N25

VDD33

TCK

modes.

JTAG serial data clock. Used in both Boundary Scan and ICE

TCK

N24

VDD33

N/A

modes.

TMS1

P25

VDD33

TCK

JTAG test mode select. Used in Boundary Scan mode.

TMS2

P26

VDD33

TCK

JTAG-ICE test mode select. Used in ICE mode.

TDO1

N23

VDD33

TCK

JTAG serial data out. Used in Boundary Scan mode.

TDO2

N22

VDD33

TCK

JTAG-ICE serial data out. Used in ICE mode.

JTAG Reset. Used in both Boundary Scan and ICE modes.

This pin should be pulled high (or left unconnected) when the

JTAG interface is in use for boundary scan or debug.

TRSTZ

M23

VDD33

Async

Connect this to ground otherwise. Failure to tie this pin low

during normal operation will cause startup and initialization

problems.

RTCK

VDD33

N/A

JTAG return clock. Used in ICE mode.

IC tri-state enable (active high). Asserting high will tri-state all

ICTSEN

M24

VDD33

Async

outputs except the JTAG interface. Requires an external

4.7 k

Ω pulldown resistor.

(1)

All JTAG signals are LVTTL compatible.

Device Test Pin Functions

I/O

CLK

I/O TYPE

DESCRIPTION

POWER

SYSTEM

NAME

NUMBER

Device manufacturing test enable. This signal must be

HW_TEST_EN

M25

VDD33

N/A

connected to an external ground for normal operation.

Peripheral Interface Pin Functions

I/O

I/O TYPE

CLK SYSTEM

DESCRIPTION

POWER

NAME

NUMBER

I2C bus 0, clock. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires

I2C0_SCL

A10

VDD33

N/A

an external pullup resistor to 3.3 V. The minimum

acceptable pullup value is 1 k

Ω resistor.

I2C bus 0, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires

I2C0_SDA

B10

VDD33

I2C0_SCL

an external pullup resistor to 3.3 V. The minimum

acceptable pullup value is 1 k

Ω resistor.

I2C bus 1, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires

I2C1_SDA (1)

E19

VDD33

I2C1_SCL

an external pullup resistor to 3.3 V. The minimum

acceptable pullup value is 1 k

Ω resistor.

I2C bus 1, clock. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires

I2C1_SCL (1)

D20

VDD33

N/A

an external pullup resistor to 3.3 V. The minimum

acceptable pullup value is 1 k

Ω resistor.

I2C bus 2, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires

I2C2_SDA (1)

C21

VDD33

I2C2_SCL

an external pullup resistor to 3.3 V. The minimum

acceptable pullup value is 1 k

Ω resistor.

(1)

This signal does not apply to the slave controller in a two controller system configuration. On the slave controller, this pin is reserved

and should be left unconnected. Refer to Typical Single Controller Chipset and Typical Two Controller Chipset for a description between

a one controller and a two controller configuration.

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