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DLPC900 Datasheet(PDF) 14 Page - Texas Instruments |
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DLPC900 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 72 page ![]() DLPC900 DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 www.ti.com Peripheral Interface Pin Functions (continued) PIN I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER This pin can be configured as GPIO 8. An external pullup GPIO_08 (1) E21 VDD33 B2 Async resistor is required when this pin is configured as open- drain. (2) This pin can be configured as GPIO 7. An external pullup GPIO_07 (1) V23 VDD33 B2 Async resistor is required when this pin is configured as open- drain. (2) This pin can be configured as GPIO 6. An external pullup GPIO_06 (1) V24 VDD33 B2 Async resistor is required when this pin is configured as open- drain. (2) This pin can be configured as GPIO 5. An external pullup GPIO_05 (1) U24 VDD33 B2 Async resistor is required when this pin is configured as open- drain. (2) This pin can be configured as GPIO 4. An external pullup GPIO_04 (1) U25 VDD33 B2 Async resistor is required when this pin is configured as open- drain. (2) This pin can be configured as GPIO 3 or PWM 3. An GPIO_PWM_03 (1) A23 VDD33 B2 Async external pullup resistor is required when this pin is configured as open-drain. (2) This pin can be configured as GPIO 2 or PWM 2. An GPIO_PWM_02 (1) A22 VDD33 B2 Async external pullup resistor is required when this pin is configured as open-drain. (2) This pin can be configured as GPIO 1 or PWM 1. An GPIO_PWM_01 (1) B21 VDD33 B2 Async external pullup resistor is required when this pin is configured as open-drain. (2) This pin can be configured as GPIO 0 or PWM 0. An GPIO_PWM_00 (1) A21 VDD33 B2 Async external pullup resistor is required when this pin is configured as open-drain. (2) (2) GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more alternative use modes, which are also software-configurable. The reset default for all GPIO signals is as an input signal. Refer to the DLPC900 Programmer's Guide (DLPU018). Trigger Control Pin Functions PIN (1) I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER In video pattern mode, this signal is used for advancing the TRIG_IN_1 AF7 VDD33 I4 Async pattern display. In video pattern mode, the rising edge of this signal is used for starting the pattern display and the falling edge is used TRIG_IN_2 H25 VDD33 I2 Async for stopping the pattern display. It works along with the software start stop command. TRIG_OUT_1 E20 VDD33 O2 Async Active high trigger output signal during pattern exposure. TRIG_OUT_2 D22 VDD33 O2 Async Active high trigger output to indicate first pattern display. (1) These signals do not apply to the slave controller in a two controller system configuration. On the slave controller, these pins are reserved and should be left unconnected. Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description between a one controller and a two controller configuration. LED Control Pin Functions PIN (1) I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER BLU_LED_PWM C20 VDD33 O2 Async Blue LED PWM current control signal GRN_LED_PWM B20 VDD33 O2 Async Green LED PWM current control signal RED_LED_PWM B19 VDD33 O2 Async Red LED PWM current control signal (1) These signals do not apply to the slave controller in a two controller system configuration. On the slave controller, these pins are reserved and should be left unconnected. Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description between a one controller and a two controller configuration. 14 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DLPC900 |
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