DLPC900 datasheet(38/72 Pages) TI1

38 / 72 page

Master Controller

Slave Controller

1280

1600

DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

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Table 3. DLPC900 – Signals

Not Covered by JTAG (1)

(continued)

SIGNAL NAME

PACKAGE BALL

TRSTZ

M23

TDO1

N23

TDO2

N22

TMS1

P25

TMS2

P26

7.3.4 Two Controller Considerations

When two DLPC900 controllers drive a single high-resolution DLP9000 DMD, each controller is used to drive half

of the DMD, as shown in Figure 16. Each controller must operate in two pixels per clock, and the pixel clock

must be maintained below the maximum two pixel per clock frequency. Only WQXGA resolution is supported

when two DLPC900 controllers are matched with a DLP9000 DMD.

Figure 16. Two Controllers Connected to DLP9000 DMD

7.4 Device Functional Modes

7.4.1 Structured Light Application

For structured light applications, the DLPC900 can be commanded to enter high speed sequential pattern modes

where a specific set of patterns are selected with a maximum of 24 bits per pixel. The bit-depth of the patterns

are then allocated into the corresponding time slots. Furthermore, an output trigger signal is also synchronized

with these time slots to indicate when the image is displayed.

This pattern mode provides the capability to display a set of patterns and signal a camera to capture these

patterns overlaid on an object. The DLPC900 controller is capable of pre-loading up to 400 1-bit binary patterns

into internal memory from the external flash memory. These pre-loaded binary patterns are then streamed to the

DMD at high speed.

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DLPC900 Datasheet(PDF) 38 Page - Texas Instruments