PEB2256HT datasheet(106/490 Pages) INFINEON

106 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

106

2002-08-27

4.5.1.1

Receive Offset Programming

Depending on the selection of the synchronization signals (SYPR or RFM), different

calculation formulas are used to define the position of the synchronization pulses. These

formulas are given below, see Figure 29 to Figure 32 for explanation. The pulse length

of SYPR and RFM is always the basic E1 bit width (488 ns), independent of the selected

system highway clock and data frequency.

SYPR Offset Calculation

Time between beginning of SYPR pulse and beginning of next frame

(time slot 0, bit 0), measured in number of SCLKR clock intervals

maximum delay: T

max =(256 × SC/SD)-1

SD:

Basic data rate; 2.048 Mbit/s

SC:

System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz

Programming value to be written to registers RC0 and RC1 (see page 239).

≤ T ≤ 4:

X = 4 - T

≤ T ≤ T

max: X = 2052 - T

RFM Offset Calculation

MP:

Marker position of RFM, counting in SCLKR clock cycles

(0 = bit 1, time slot 0, channel phase 0)

SC = 2.048 MHz:

≤ MP ≤ 255

SC = 4.096 MHz:

≤ MP ≤ 511

SC = 8.192 MHz:

≤ MP ≤ 1023

SC = 16.384 MHz:

≤ MP ≤ 2047

SD:

Basic data rate; 2.048 Mbit/s

SC:

System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz

Programming value to be written to registers RC0 and RC1 (see page 239).

≤ MP ≤ 2045: X = MP + 2

2046

≤ MP ≤ 2047: X = MP - 2046

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