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PEB2256HT Datasheet(PDF) 105 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 105 Page - Infineon Technologies AG |
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105 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 105 2002-08-27 4.5.1 Receive System Interface (E1) Figure 28 Receive System Interface Clocking (E1) ITD10951 FRAME 1 FRAME 2 FRAME 3 FRAME 15 FRAME 16 FRAME 1 FRAME 2 FRAME 15 Bit 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 1 Bit 0 Bit 255 T Multi Frame 1 Multi Frame 2 4 Mbit Interface 2 Mbit Interface Programmable via RC0/1 RDO RMFB SYPR SYPR SCLKR 8.192 MHz 2.048 MHz SCLKR 2 Mbit/s Data Rate RDO/RSIG TS0 RDO/RSIG (SCLKR = 8.192 MHz) 4 Mbit/s Data Rate DLR Sa-Bit Marker XC0 . SA8E-SA4E Receive Frame Marker RFM RC0/1 RSIGM Time-Slot Marker RTR1...4 4 Mbit/s Data Rate (SCLKR = 8.192 MHz) RDO/RSIG Trigger Edge Edge Sample marks any Sa Bit bit position marks any marks any Time-Slot 4 Mbit Interface 2 Mbit Interface Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1) only falling trigger edge shown, depending on Bit SIC3.RESR 1) |
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