PEB2256HT datasheet(178/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

178

2002-08-27

FS/DL data on system transmit highway (XDI), time slot 0:

Figure 69

Transmit FS/DL Bits on XDI (T1/J1)

5.5.2.1

Transmit Offset Programming

The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in 1.544-

MHz mode or the E1 bit width (488 ns) in 2.048-MHz mode.

This chapter describes the system highway operation in 1.544-MHz mode only. If the

system highway is operated in 2.048-MHz mode, the description given in

Chapter 4.5.2.1 on page 111 applies.

SYPX Offset Calculation

Time between the active edge of SCLKX after SYPX pulse begin and beginning

of the next frame (F-bit, channel phase 0), measured in number of SCLKX clock

intervals; maximum delay: T

max =(200 × SC/BF)-(7 × SC/BF)-1

BF:

Basic frequency; 1.544 Mbit/s

SC:

System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz

Programming value to be written to registers RC0 and RC1 (see page 356).

≤ T ≤ 4:

X = 3 - T + (7

× SC/BF)

≤ T ≤ T

max: X = (200 × SC/BF)-T+ 3

ITD06460

FS/DL Time-Slot

MSB

LSB

FS/DL Data Bit

FS/DL

PEB2256HT Datasheet(PDF) 178 Page - Infineon Technologies AG