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Z80 Datasheet(PDF) 136 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 136 Page - Zilog, Inc. |
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136 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Table 11 and Table 12 illustrate how the pipelining of data affects the number of bytes transferred or searched in the various classes, modes, and circumstances of operation. In most cases, the number of bytes transferred in a transfer operation that stops at end-of-block is one more than the programmed block length. When the pulse-generation feature is used, the contents of the pulse control byte in WR4 are compared with the lower byte of the byte counter after each byte is transferred. Port A Address Counter (RR3, RR4) This 16-bit counter is loaded from the Port A starting address register in WR0 by the LOAD command. It increments, decrements, or remains fixed according to the specifications in WR1. Table 11 and Table 12 show how this counter reads under various transfer or search conditions. Port B Address Counter (RR5, RR6) This counter is identical to the Port A address counter just described. If either Port A or Port B is a fixed-address destination port, it must be programmed as described in “Fixed-Address Destination Ports” on page 121 to function properly. Review of Programming Sequences This section describes programming the DMA in both the general and in application-specific cases. Also, see Table 16 on page 127 for a sample DMA Program. DMA Initialization Program all registers to be used in the DMA at power-up. None of these registers contain useful defaults. This procedure includes the enabling of |
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