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Z80 Datasheet(PDF) 132 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 132 Page - Zilog, Inc. |
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132 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Enable DMA (87) This command allows the DMA to request the system bus and proceed with its operation if all other functional conditions are met, for example, if the Ready line is active or the FORCE READY condition is present. This command, and bit 6 of WR3, are the only control bytes that do not disable the DMA. All other control bytes written to the DMA automatically disable the DMA. Therefore, the ENABLE DMA command is always required as the last command after writing or reading any other bytes to or from the DMA. This command enables the DMA’s bus request logic. It does not affect interrupt logic and it does not reset any functions or latches. This bus- request-enabling function is duplicated in bit 6 of WR3. In an interrupt service routine, the ENABLE DMA command must be the last command to the DMA before the CPU executes its return-from- interrupt instruction. Disable DMA (83) This command prevents the DMA from requesting the bus. It is used to stop DMA action for external reasons, such as a pending power-out, and in the special case of reinitializing the status byte after a stop on end-of-block or a stop on byte match (see the REINITIALIZE STATUS BYTE command). Read Registers Process Read registers by first writing a command to the DMA, then by reading either immediately or later. Accomplish CPU reads by addressing the DMA as an I/O device using input instructions (such as INIR for the Z80 CPU). Commands written to the DMA can be either of the following: |
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