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Z80 Datasheet(PDF) 128 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 128 Page - Zilog, Inc. |
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128 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access end of the service routine, the CPU writes a RESET AND DISABLE INTERRUPTS command, then an ENABLE INTERRUPTS command, and then an ENABLE DMA command before executing its return-from- interrupt instruction. This command, when followed by an ENABLE INTERRUPTS command, takes the place of the Z80 RETI instruction. It is not needed in a Z80 envi- ronment. Because RESET AND DISABLE INTERRUPTS unforces a FORCED-READY condition, the RESET AND DISABLE INTERRUPTS must precede a FORCE READY command when the latter is used. Enable After RETI (B7) This commandis usedonlywhen the DMA is operatedin the InterruptOn Ready mode (programmed in WR4). It enables the DMA to request the bus again after returning from an interrupt. This command is always used in Z80 CPU environments to get further bus requesting after an Interrupt on Ready. It is sometimes used in other environments, such as the 8080. An Interrupt on Ready (IOR) latch is set during such an interrupt. This latch prevents the DMA from requesting the bus from the time the Ready line goes active until the time the latch is reset by the ENABLE AFTER RETI command (in Z80 and some other environments, there is an overlap in bus- request prevention by the IOR and the IUS latches). In a Z80 CPU interrupt service routine, the order of DMA commands and CPU instructions MUST be: 1. • 2. • 3. • 4. ENABLE AFTER RETI command 5. ENABLE DMA command |
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