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Z80 Datasheet(PDF) 127 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 127 Page - Zilog, Inc. |
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127 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Enable Interrupts (AB) See the preceding description of DISABLE INTERRUPTS. A Z80 CPU environment uses this command at power-up to enable the interrupt logic at the beginning (the DMA comes up with this logic disabled). It is not needed, however, to enable subsequent interrupts because this function is provided for by the CPU’s fetching and the DMA’s decoding of the RETI instruction. The only exception is when the DISABLE INTERRUPTS command is used; the ENABLE INTERRUPTS command must also be used to begin DMA operations again. Any conditions selected to cause an interrupt are latched in the DMA even when interrupts are disabled. They can then cause a later interrupt after interrupts are reenabled. The ENABLE INTERRUPTS command must not be written until after the DMA has been configured and the REINITIALIZE STATUS BYTE command has been written. This command has the same effect as writing a 1tobit 5 of WR3. Reset and Disable Interrupts (A3) This command is useful in CPU environments such as the 8080 and 8085 where there is an interrupt acknowledge function but no RETI instruction, as in the Z80 CPU. This command accomplishes four functions: • Resets the Interrupt Under Service (IUS) latch • Resets the Interrupt Pending (IP) latch • Unforces an internal FORCE READY condition • Disables further interrupts by the DMA (same as the DISABLE INTERRUPTS command) In the non-Z80 environment just described, it would be used as follows: after the DMA interrupt is received and acknowledged, the interrupt vector is sent to the CPU, which branches to the service routine. Near the |
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