| Electronic Components Datasheet Search |
|
Z80 Datasheet(PDF) 123 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z80 Datasheet(HTML) 123 Page - Zilog, Inc. |
|
123 / 330 page ![]() < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Figure 45. Write Register 5 Group Write Register 6 Group The base register byte for this group has bits 7, 1, and 0 set to one, which Figure 46 depicts. The remaining bits specify 16 commands that are commonly used after DMA initialization (for example, within CPU interrupt service routines), and to point to a read mask for the read registers. Each of these commands, except the ENABLE DMA command, disables the DMA. Therefore, the ENABLE DMA command must be the last command written before DMA bus requests can begin. Reset (C3) This command is used at power-up and when aborting a program sequence to do the following: • Disable interrupt and bus-request logic • Reset interrupt latches • Unforce a FORCE READY condition • Reset the Auto Repeat function (see WR5) • Reset the Wait function (See WR5) D7 D6 D5 D4 D3 D2 D1 D0 Base Register Byte 0 = Ready Active Low 1 = Ready Active High 10 0 10 0 = Stop on End-of-Block 1 = Auto Restart on End-of-Block 0 =CE Only 1 =CE/WAIT Only |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |