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Z80 Datasheet(PDF) 122 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 122 Page - Zilog, Inc. |
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122 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access End-of-Block Action Bit 5 specifies either a stop (bus release) or an auto repeat at the end of the blocklengthprogrammedinWR0. Tointerrupt at the end of a block (WR4), bit 5 should be 0 because the DMA must reset the end-of-block status bit to proceed with a new block. In Auto Restart, the end-of-block status bit is also reset. CE/WAIT Line Use Bit 4 specifies that the DMA’s CE/WAIT line is to be used in one of two ways: CE Only The CE/WAIT line functions only as a chip enable line, allowing CPU writing and reading of control/status bytes when the DMA is not bus master. See the “Applications” chapter for the method by which this time is decoded from the address bus. CE/WAIT Multiplex This line functions as described in “CE only” above, when the DMA is not bus master. When the DMA has the bus, however, the line allows external Wait inputs from external logic to extend the DMA's cycle programmed in WR1 and/or WR2. See the “Applications” chapter for hardware interfacing of this option. Ready-Line State Bit 3 specifies that the DMA interprets the Ready (RDY) line as active when High or active when Low. This allows flexibility in interfacing to a variety of other devices. |
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