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Z80 Datasheet(PDF) 118 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 118 Page - Zilog, Inc. |
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118 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access DMA Enable A1 in bit 6 of the base register enables the DMA to request the bus. This function duplicates the ENABLE DMA command in WR6 and is used as the last control byte written to the DMA prior to allowing the DMA to usurp the bus from the CPU. The ENABLE DMA command is often better for this purpose. Figure 43. Write Register 3 Group Write Register 4 Group Bits 7, 1, and 0, which Figure 44 shows, select the base register byte for this group. The group specifies the following characteristics: Operating Mode Bits 6 and 5 of the base register specify the operating mode as Byte, Burst, or Continuous. For a review of these modes, see Figure 41 through Figure 44, Table 13 and Table 15. D7 D6 D5 D4 D3 D2 D1 D0 Base Register Byte Mask Byte (0 = Compare) 00 0 DMA Enable = 1 Interrupt Enable = 1 1 = Stop on Match Match Byte |
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