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Z80 Datasheet(PDF) 117 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 117 Page - Zilog, Inc. |
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117 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Stop on Match Setting bit 2 of the base register byte to 1 causes the DMA to stop and release the bus when a data byte matches the match byte, which is described later. A search or transfer/search operation must be specified in WR0 to make this bit valid when set. If this bit is 0 (no stop on match), a status flag is still set in the status byte when a match occurs and there still remains the option of interrupting on match (see WR4). No stop or interrupt on match in the search class is used to obtain simultaneous transfers without searching actions. Match Byte When bit 4 of the base register is set to 1, the match byte that is compared with every data byte searched must be specified. A search operation must be specified in WR0 to make this bit valid, as shown in the following function. Mask Byte When bit 3 is set to 1, the mask byte must be subsequently specified. Bit positions that contain 1s in the mask byte cause comparisons at those same bit positions in the match byte (see preceding paragraph) to be ignored. For example, if the mask byte is 00001111, only the high four bits of the match byte is compared to the data bytes being searched. Interrupt Enable A 1 in bit 5 of the base register enables the DMA to generate an interrupt. This function duplicates the ENABLE INTERRUPTS command in WR6. |
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