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Z80 Datasheet(PDF) 195 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 195 Page - Zilog, Inc. |
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195 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output Parallel Input/Output OVERVIEW The Z80 Parallel Input/Output (PIO) Circuit is a programmable, two-port device that provides a TTL-compatible interface between peripheral devices and the Z80 CPU. The CPU configures the Z80 PIO to interface with a wide range of peripheral devices with no other external logic required. Typical peripheral devices that are fully compatible with the Z80 PIO include most keyboards, paper tape readers and punches, printers, and PROM programmers. The Z80 PIO package is available in 40-pin DIP, 44- pin PLCC, or 44-pin QFP. The CMOS version is available in all three pack- age configurations. The NMOS version is available in 40-pin DIP and 44- pin PLCC. One unique feature that separates the Z80 PIO from other interface control- lers is that all data transfers between the peripheral device and the CPU is under total interrupt control. The PIO interrupt logic allows full use of the efficient interrupt capabilities of the Z80 CPU during I/O transfers. All logic necessary to implement a fully nested interrupt structure is included in the PIO, requiring no additional circuits. Another unique feature is that the PIO can be programmed to interrupt the CPU on the occurrence of speci- fied status conditions in the peripheral device. For example, the PIO can be programmed to interrupt when any specified peripheral alarm conditions occur. This interrupt capability reduces the amount of time spent by the pro- cessor polling peripheral status. FEATURES • Two independent 8-Bit bidirectional peripheral interface ports with handshake data transfer control • Interrupt-driven handshake for fast response |
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