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Z80 Datasheet(PDF) 207 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 207 Page - Zilog, Inc. |
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207 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output Figure 6. 40-Pin DIP Pin Assignments PROGRAMMING THE PIO Reset The Z80 PIO automatically enters a reset state when power is applied. The reset state performs the following functions: 1. Both port mask registers are reset to inhibit all port data bits. 2. Port data bus lines are set to a high-impedance state and the Ready handshake signals are inactive (Low). Mode 1 is automatically selected. 3. The vector address registers are not reset. 4. Both port interrupt enable flip-flops are reset. 5. Both port output registers are reset. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Z80 PIO D2 D7 D6 CE C/D B/A PA7 PA6 PA5 PA4 GND PA3 PA2 PA1 PA0 ASTB BSTB ARDY D0 D1 D3 D4 D5 M1 IORQ RD PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 +5V CLK IEI INT IEO BRDY |
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