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Z80 Datasheet(PDF) 204 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 204 Page - Zilog, Inc. |
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204 / 330 page ![]() <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output BRDY Register B Ready (output, active High). The meaning of this signal is similar tothatof A Readywiththe followingexception:Inthe Port Abidi- rectional mode, this signal is High when the Port A input register is empty and ready to accept data from the peripheral device. Figure 3. PIO Pin Functions Z80–PIO Port A I/O A0 A1 A2 A3 A4 A5 A6 A7 ARDY ASTB B0 B1 B2 B3 B4 B5 B7 BRDY BSTB B6 15 14 13 12 10 9 8 7 18 16 31 32 33 34 21 17 27 28 29 30 Port B I/O CPU Data D0 D1 A2 D3 D4 D5 D6 D7 Port B/A SEL Control/Data SEL Chip Enable M1 IORQ RD +5V Φ INT GND 19 20 1 40 39 38 3 2 6 5 26 11 25 23 4 37 36 35 INT Enable in 24 INT Enable out 22 BUS PIO Control Interrupt Control |
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