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Z80 Datasheet(PDF) 200 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 200 Page - Zilog, Inc. |
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200 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output PIN DESCRIPTION Figure 3 illustrates a diagram of the Z80 PIO pin configuration. This section describes the function of each pin. D7-D0 Z80 CPU Data Bus (bidirectional, tristate). This bus is used to transfer all data and commands between the Z80 CPU and the Z80 PIO. D0 is the least-significant bit of the bus. B/A Sel Port B or A Select (input, active High). This pin defines which port is accessed during a data transfer between the Z80 CPU and the Z80 PIO. A Low level on this pin selects Port A while a High level selects Port B. Often, Address bit A0 from the CPU is used for this selection function. C/D Sel Control or Data Select (input, active High). This pin defines the type of data transfer to be performed between the CPU and the PIO. A High level on this pin during a CPU write to the PIO causes the Z80 data bus to be interpreted as a command for the port selected by the B/A Select line. A Lowlevel on this pinmeansthatthe Z80 data bus is beingusedtotransfer data between the CPU and the PIO. Often, Address bit Al from the CPU is used for this function. CE Chip Enable (input, active Low). A Low level on this pin enables the PIO to accept command or data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This signal is generally a decode of four I/O port numbers that encompass Ports A and B, data, and control. |
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