Z80 datasheet(242/330 Pages) ZILOG

242 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

222

ARCHITECTURE

Overview

The device internal structure includes a Z80 CPU interface, internal control

and interrupt logic, and two full-duplex channels. Associated with each

channel are read and write registers, and discrete control and status logic

that provides the interface to modems or other external devices.

The read and write register group includes five 8-bit control registers, two

sync-character registers, and two status registers. The interrupt vector is

written into an additional 8-bit register (Write Register 2) in Channel B that

may be read through Read Register 2 in Channel B. The registers for both

channels are designated as follows:

WR7–WR0 — Write Registers 0 through 7

RR2–RR0 — Read Registers 0 through 2

The bit assignment and functional grouping of each register is configured to

simplify and organize the programming process. Table 1 and Table 2 illus-

trate the functions assigned to each read or write register.

The logic for both channels provides formats, synchronization, and valida-

tion for data transferred to and from the channel interface. The modem

control inputs Clear to Send (CTS) and Data Carrier Detect (DCD)are

monitored by the discrete control logic under program control. All the

modem control signals are general purpose and can be used for functions

other than modem control.

For automatic interrupt vectoring, the interrupt control logic determines

which channel and which device within the channel has the highest priority.

Priority is fixed with Channel A assigned a higher priority than Channel B;

Receive, Transmit and External/Status interrupts are prioritized in that

order within each channel.

Z80 Datasheet(PDF) 242 Page - Zilog, Inc.