Z80 datasheet(245/330 Pages) ZILOG

245 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

225

during which the Z80 SIO tries to match the assembled character in the

receive shift register with the nag pattern in WR7. When the first flag char-

acter is recognized, all subsequent data is routed through the same path,

regardless of character length.

Although the same CRC checker is used for both SDLC and synchronous

data, the data path taken for each mode is different. In Bisync protocol, a

byte-oriented operation requires that the CPU decide to include the data

character in CRC. To allow the CPU ample time to make this decision, the

Z80 SIO provides an 8-bit delay for synchronous data. In the SDLC mode,

no delay is provided because the Z80 SIO contains logic that determines the

bytes on which CRC is calculated.

The transmitter has an 8-bit transmit data register that is loaded from the

internal data bus and a 20-bit transmit shift register that can be loaded from

WR6, WR7, and the transmit data register. WR6 and WR7 contain sync

characters in the Monosync or Bisync modes, or address field (one char-

acter long) and flag respectively in the SDLC mode. During Synchronous

modes, information contained in WR6 and WR7 is loaded to the transmit

shift register at the beginning of the message and, as a time filler, in the

middle of the message if a Transmit Underrun condition occurs. In the

SDLC mode, the flags are loaded to the transmit shift register at the begin-

ning and end of message.

Asynchronous data in the transmit shift register is formatted with start and

stop bits and is shifted out to the transmit multiplexer at the selected clock

rate. Synchronous (Monosync or Bisync) data is shifted out to the transmit

multiplexer and also to the CRC generator at the x1 clock rate.

SDLC/HDLC data is shifted out through the zero insertion logic, which is

disabled while the flags are sent. For all other fields (address, control, and

frame check) a 0 is inserted following five contiguous 1s in the data stream.

The CRC generator result for SDLC data is also routed through the zero

insertion logic.

Z80 Datasheet(PDF) 245 Page - Zilog, Inc.