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Z80 Datasheet(PDF) 244 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 244 Page - Zilog, Inc. |
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244 / 330 page ![]() <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Serial Input/Output 224 entered in the 3-bit buffer if the data has a character length of seven or eight bits, or is entered in the 8-bit receive shift register if the data has a length of five or six bits. In the Synchronous mode, the data path is determined by the phase of the receive process currently in operation. A Synchronous Receive operation begins with the receiver in the Hunt phase, during which the receiver searches the incoming data stream for a bit pattern that matches the prepro- grammed sync characters for flags in the SDLC mode. If the device is programmed for Monosync Hunt, a match is made with a single sync char- acter stored in WR7. In Bisync Hunt, a match is made with dual sync char- acters stored in WR6 and WR7. In either case, the incoming data passes through the receive sync register, and is compared against the programmed sync character in WR6 or WR7. In the Monosync mode, a match between the sync character programmed to WR7 and the character assembled in the receive sync register establishes synchronization. In the Bisync mode, however, incoming data is shifted to the receive shift register while the next eight bits of the message are assembled in the receive sync register. The match between the assembled character in the receive sync registers with the programmed sync character in WR6 and WR7 establishes synchronization. When synchronization is established, incoming data bypasses the receive sync register and directly enters the 3-bit buffer. In the SDLC mode, incoming data first passes through the receive sync register, which continuously monitors the receive data stream and performs zero deletion when indicated. Upon receiving five contiguous 1s, the sixth bit is inspected. If the sixth bit is a 0, it is deleted from the data stream. If the sixth bit is a 1, the seventh bit is inspected. If the seventh bit is a 0, a Flag sequence has been received; if it is a 1, an Abort sequence has been received. The reformatted data enters the 3-bit buffer and is transferred to the receive shift register. The SDLC receive operation also begins in the Hunt phase, |
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