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CS8900A Datasheet(PDF) 70 Page - Cirrus Logic |
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CS8900A Datasheet(HTML) 70 Page - Cirrus Logic |
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70 / 128 page  70 DS271PP3 CS8900A Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATA SHEET 4.4.23 Register 1C: AUI Time Domain Reflectometer (Read-only, Address: PacketPage base + 013Ch) The TDR counter (Bits 6 through F) is a time domain reflectometer useful in locating cable faults in 10BASE-2 and 10BASE-5 coax networks. It counts at a 10 MHz rate from the beginning of transmission on the AUI to when a col- lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read. 011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status Register. When reading this register, these bits will be 011100, where the LSB corresponds to Bit 0. AUI-Delay The upper ten bits contains the number of 10 MHz clock periods between the beginning of transmission on the AUI to when a collision or Loss-of-Carrier error occurs. Reset value is: 0000 0000 0001 1100 765 4321 0 AUI Delay 011100 F E DCBA 9 8 AUI Delay |
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