CS8900A datasheet(17/128 Pages) CIRRUS

17 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8900A performs

two basic functions: Ethernet packet transmission

and reception. Before transmission or reception is

possible, the CS8900A must be configured.

3.1.1 Configuration

The CS8900A must be configured for packet trans-

mission and reception at power-up or reset. Various

parameters must be written into its internal Config-

uration and Control registers such as Memory Base

Address; Ethernet Physical Address; what frame

types to receive; and which media interface to use.

Configuration data can either be written to the

CS8900A by the host (across the ISA bus), or load-

ed automatically from an external EEPROM. Oper-

ation can begin after configuration is complete.

Section 3.3 on page 19 and Section 3.4 on page 21

describe the configuration process in detail.

Section 4.4 on page 47 provides a detailed descrip-

tion of the bits in the Configuration and Control

Registers.

3.1.2 Packet Transmission

Packet transmission occurs in two phases. In the

first phase, the host moves the Ethernet frame into

the CS8900A’s buffer memory. The first phase be-

gins with the host issuing a Transmit Command.

This informs the CS8900A that a frame is to be

transmitted and tells the chip when to start trans-

mission (i.e. after 5, 381, 1021 or all bytes have

been transferred) and how the frame should be sent

(i.e. with or without CRC, with or without pad bits,

etc.). The Host follows the Transmit Command

with the Transmit Length, indicating how much

buffer space is required. When buffer space is

available, the host writes the Ethernet frame into

the CS8900A’s internal memory, either as a Mem-

ory or I/O space operation.

In the second phase of transmission, the CS8900A

converts the frame into an Ethernet packet then

transmits it onto the network. The second phase be-

gins with the CS8900A transmitting the preamble

and Start-of-Frame delimiter as soon as the proper

number of bytes has been transferred into its trans-

mit buffer (5, 381, 1021 bytes or full frame, de-

pending on configuration). The preamble and Start-

of-Frame delimiter are followed by the Destination

Address, Source Address, Length field and LLC

data (all supplied by the host). If the frame is less

than 64 bytes, including CRC, the CS8900A adds

pad bits if configured to do so. Finally, the

CS8900A appends the proper 32-bit CRC value.

The Section 5.7 on page 99 provides a detailed de-

scription of packet transmission.

3.1.3 Packet Reception

Like packet transmission, packet reception occurs

in two phases. In the first phase, the CS8900A re-

ceives an Ethernet packet and stores it in on-chip

memory. The first phase of packet reception begins

with the receive frame passing through the analog

front end and Manchester decoder where Manches-

ter data is converted to NRZ data. Next, the pream-

ble and Start-of-Frame delimiter are stripped off

and the receive frame is sent through the address

filter. If the frame’s Destination Address matches

the criteria programmed into the address filter, the

packet is stored in the CS8900A’s internal memo-

ry. The CS8900A then checks the CRC, and de-

pending

the

configuration,

informs

the

processor that a frame has been received.

In the second phase, the host transfers the receive

frame across the ISA bus and into host memory.

Receive frames can be transferred as Memory

space operations, I/O space operations, or as DMA

operations using host DMA. Also, the CS8900A

provides the capability to switch between Memory

or I/O operation and DMA operation by using

Auto-Switch DMA and StreamTransfer.

The Section 5.2 on page 79 through Section 5.6 on

page 96 provide a detailed description of packet re-

ception.

CS8900A Datasheet(PDF) 17 Page - Cirrus Logic

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