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TMS320VC5502 Datasheet(PDF) 119 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 189 page  www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Table 3-71. UART WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE(1) 0x9C00 URRBR/ Receive Buffer Register xxxx xxxx URTHR/ Transmit Holding Register URDLL(2) Divisor Latch LSB Register 0x9C01 URIER/ Interrupt Enable Register 0000 0000 URDLM(3) Divisor Latch MSB Register 0x9C02 URIIR/ Interrupt Identification Register 0000 0001 URFCR(4) FIFO Control Register 0000 0000 0x9C03 URLCR Line Control Register 0000 0000 0x9C04 URMCR Modem Control Register 0000 0000 0x9C05 URLSR Line Status Register 0110 0000 0x9C07 URSCR Scratch Register xxxx xxxx 0x9C08 URDLL(2) Divisor Latch LSB Register – 0x9C09 URDLM(3) Divisor Latch MSB Register – 0x9C0A URPID1 Peripheral ID Register (LSW) – 0x9C0B URPID2 Peripheral ID Register (MSW) – 0x9C0C URPECR Power and Emulation Control Register 0000 0000 0000 0000 (1) x denotes a "don't care." (2) The registers URRBR, URTHR, and URDLL share one address. URDLL also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URRBR and URTHR are always selected at the shared address. • If DLAB = 0: Read Only: URRBR Write Only: URTHR • If DLAB = 1: Read/Write: URDLL (3) The registers URIER and URDLM share one address. URDLM also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URIER is always selected at the shared address. • If DLAB = 0: Read/Write: URIER • If DLAB = 1: Read/Write: URDLM (4) The registers URIIR and URFCR share one address. • Read Only: URIIR • Write Only: URFCR Table 3-72. External Bus Selection WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE 0x6C00 XBSR External Bus Selection Register 0000 0000 0000 0000 0x8800 XBCR External Bus Control Register 0000 0000 0000 0000 Table 3-73. Clock Mode Register WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE 0x8C00 CLKMD Clock Mode Control Register 0000 0000 0000 0000 Functional Overview 119 |
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