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3.17.2

Interrupt Timing

3.17.3

Interrupt Acknowledge

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The bit layouts of these registers for each interrupt are shown in Figure 3-51 and Figure 3-52. For more

information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide

(literature number SPRU371).

RINT2/

INT3/

DMAC5

DMAC4

XINT2

DSPINT

DMAC1

Reserved

UART

WDTINT(1)

R/W, 0

XINT1

RINT1

RINT0

TINT0

INT2

INT0

Reserved

R/W, 0

R, 0

LEGEND: R = Read, W = Write, n = value at reset

(1)

WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

Figure 3-51. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

Reserved

RTOS

DLOG

BERR

R, 0

R/W, 0

I2C

TINT1

DMAC3

DMAC2

INT4

DMAC0

XINT0

INT1

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-52. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer.

The interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of

1-0-0-0 on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low

pulse duration on the external interrupts on the 5502 is three CPU clock periods.

TIM0, TIM1, WDTOUT, and HPI.HAS can be configured to generate interrupts to the CPU. When they are

used for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will

generate TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to

pass between consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will

be ignored(i.e., a sequence of 0-1-1-1-0 on consecutive cycles is required for consecutive interrupts). For

more information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and

to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number

SPRU620) for the HPI pin.

The IACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the

interrupt vector location designated on the address bus. As the CPU fetches the first word or the software

vector, it generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go

low for a total of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU

will not jump to an interrupt service routine if the appropriate interrupt enable bit is not set; consequently,

the IACK pin will not go low when the interrupt is generated.

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TMS320VC5502 Datasheet(PDF) 122 Page - Texas Instruments

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