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TMS320VC5502 Datasheet(PDF) 121 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 189 page  www.ti.com 3.17.1 IFR and IER Registers TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Table 3-77. Interrupt Table (continued) SOFTWARE LOCATION NAME (TRAP) PRIORITY FUNCTION (HEX BYTES) EQUIVALENT DSPINT SINT10 50 14 Interrupt from host INT3/WDTINT(1) SINT11 58 15 External interrupt #3 or Watchdog timer interrupt RINT2 SINT12 60 17 McBSP #2 receive interrupt XINT2 SINT13 68 18 McBSP #2 transmit interrupt DMAC4 SINT14 70 21 DMA Channel #4 interrupt DMAC5 SINT15 78 22 DMA Channel #5 interrupt INT1 SINT16 80 4 External interrupt #1 XINT0 SINT17 88 8 McBSP #0 transmit interrupt DMAC0 SINT18 90 12 DMA Channel #0 interrupt – SINT19 98 16 Software interrupt #19 DMAC2 SINT20 A0 19 DMA Channel #2 interrupt DMAC3 SINT21 A8 20 DMA Channel #3 interrupt TINT1 SINT22 B0 23 Timer #1 interrupt IIC SINT23 B8 24 I2C interrupt BERR SINT24 C0 2 Bus Error interrupt DLOG SINT25 C8 25 Data Log interrupt RTOS SINT26 D0 26 Real-time Operating System interrupt – SINT27 D8 27 Software interrupt #27 – SINT28 E0 28 Software interrupt #28 – SINT29 E8 29 Software interrupt #29 – SINT30 F0 30 Software interrupt #30 SINT31 F8 31 Software interrupt #31 (1) WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR. The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are currently pending. The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1) is used and DBIER0/1 are ignored. A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an interrupt enable register (IER0 or IER1). Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time emulation mode. A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1. Functional Overview 121 |
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