DM9000 datasheet(3/54 Pages) ETC

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DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F02

June 26, 2002

9. Functional Description ........................................31

9.1 Host Interface....................................................31

9.2 Direct Memory Access Control .........................31

9.3 Packet Transmission.........................................31

9.4 Packet Reception..............................................31

9.5 100Base-TX Operation .....................................32

9.5.1 4B5B Encoder................................................32

9.5.2 Scrambler.......................................................32

9.5.3 Parallel to Serial Converter ............................32

9.5.4 NRZ to NRZI Encoder....................................32

9.5.5 MLT-3 Converter............................................32

9.5.6 MLT-3 Driver ..................................................32

9.5.7 4B5B Code Group..........................................33

9.6 100Base-TX Receiver.......................................34

9.6.1 Signal Detect..................................................34

9.6.2 Adaptive Equalization ....................................34

9.6.3 MLT-3 to NRZI Decoder.................................34

9.6.4 Clock Recovery Module .................................34

9.6.5 NRZI to NRZ ..................................................34

9.6.6 Serial to Parallel.............................................34

9.6.7 Descrambler...................................................34

9.6.8 Code Group Alignment ..................................35

9.6.9 4B5B Decoder................................................35

9.7 10Base-T Operation..........................................35

9.8 Collision Detection ............................................35

9.9 Carrier Sense....................................................35

9.10 Auto-Negotiation .............................................35

9.11 Power Reduced Mode ....................................36

9.11.1 Power Down Mode.......................................36

9.11.2 Reduced Transmit Power Mode ..................36

10. DC and AC Electrical Characteristics ...............37

10.1 Absolute Maximum Rating (25∘C) ................37

10.2 Operating Conditions ......................................37

10.3 DC Electrical Characteristics ..........................38

10.4 AC Electrical Characteristics & Timing

Waveforms.......................................................39

10.4.1 TP Interface .................................................39

10.4.2 Oscillator/ Crystal Timing.............................39

10.4.3 Processor Register Read Timing.................39

10.4.4 Processor Register Write Timing .................40

10.4.5 External MII Interface Transmit Timing........41

10.4.6 External MII Interface Receive Timing.........41

10.4.7 MII Management Interface Timing ...............42

10.4.8 EEPROM Interface Timing ..........................42

11. Application Notes ..............................................43

11.1 Network Interface Signal Routing ...................43

11.2 10Base-T/100Base-TX Application Figure 11-1

.........................................................................43

11.3 10Base-T/100Base-TX (Power Reduction

Application)　Figure 11-2................................44

11.4 Power Decoupling Capacitors Figure 11-3 .....45

11.5 Ground Plane Layout Figure 11-4 ..................46

11.6 Power Plane Partitioning Figure 11-5 .............47

11.7 Magnetics Selection Guide .............................48

11.8 Crystal Selection Guide Figure 11-6...............48

11.9 Application of reverse MII Figure 11-7............49

12. Package Information .........................................50

12.1 LQFP 100L Outline Dimensions .....................50

13. Appendix ...........................................................51

14. Order Information..............................................53

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