DM9000 datasheet(20/54 Pages) ETC

20 / 54 page

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F02

June 26, 2002

6.30 Memory data write command with address increment Register (F8H)

Bit

Name

Default

Description

7:0

MWCMD

X,WO

Write Data to TX SRAM

After the write of this command, the write pointer is increased by 1,2, or 4, depends

on the operator mode. (8-bit, 16-bit,32-bit respectively)

6.31 Memory data write_address Register (FAH~FBH)

Bit

Name

Default

Description

7:0

MDRAH

00H,R/W

Memory Data Write_ address High Byte

7:0

MDRAL

00H,R/W

Memory Data Write_ address Low Byte

6.32 TX Packet Length Register (FCH~FDH)

Bit

Name

Default

Description

7:0

TXPLH

X,R/W

TX Packet Length High byte

7:0

TXPLL

X,,R/W

TX Packet Length Low byte

6.33 Interrupt Status Register (FEH)

Bit

Name

Default

Description

7:6

IOMODE

0, RO

Bit 7 Bit 6

16-bit mode

32-bit mode

8-bit mode

Reserved

5~4

RESERVED

0,RO

Reserved

ROOS

0,RW/C1

Receive Overflow Counter Overflow Latch

ROS

0,RW/C1

Rx Overflow Latch

PTS

0,RW/C1

Packet Transmitted Latch

PRS

0,RW/C1

Packet Received Latch

6.34 Interrupt Mask Register (FFH)

Bit

Name

Default

Description

PAR

0,RW

Enable the SRAM read/write pointer to automatically return to the start address

when pointer addresses are over the SRAM size. Driver needs to set. When driver

sets this bit, REG_F5 will set to 0Ch automatically

6~4

RESERVED

0,RO

Reserved

ROOM

0,RW

Enable Receive Overflow Counter Overflow Latch

ROM

0,RW

Enable RX Overflow Latch

PTM

0,RW

Enable Packet Transmitted Latch

PRM

0,RW

Enable Packet Received Latch

DM9000 Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers

DM9000 Datasheet(HTML) 20 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL