DM9000 datasheet(16/54 Pages) ETC

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DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F02

June 26, 2002

6.10 Flow Control Threshold Register ( 09H )

Bit

Name

Default

Description

7:4

HWOT

3H, RW

RX FIFO High Water Overflow Threshold

Send a pause packet with pause_ time=FFFFH when the RX RAM free space is

less than this value., If this value is zero, its means no free RX SRAM space.

Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)

3:0

LWOT

8H, RW

RX FIFO Low Water Overflow Threshold

Send a pause packet with pause_time=0000 when RX SRAM free space is larger

than this value. This pause packet is enabled after the high water pause packet is

transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM size

(1 unit=1K bytes)

6.11 RX/TX Flow Control Register ( 0AH )

Bit

Name

Default

Description

TXP0

0,RW

TX Pause Packet

Auto clears after pause packet transmission completion. Set to TX pause packet

with time = 0000h

TXPF

0,RW

TX Pause packet

Auto clears after pause packet transmission completion. Set to TX pause packet

with time = FFFFH

TXPEN

0,RW

Force TX Pause Packet Enable

Enables the pause packet for high/low water threshold control

BKPA

0,RW

Back Pressure Mode

This mode is for half duplex mode only. It generates a jam pattern when any packet

comes and RX SRAM is over BPHW

BKPM

0,RW

Back Pressure Mode

This mode is for half duplex mode only. It generates a jam pattern when a packet’s

DA matches and RX SRAM is over BPHW

RXPS

0,R/C

RX Pause Packet Status, latch and read clearly

RXPCS

0,RO

RX Pause Packet Current Status

0FLCE

0,RW

Flow Control Enable

Set to enable the flow control mode (i.e. to disable TX function)

6.12 EEPROM & PHY Control Register ( 0BH )

Bit

Name

Default

Description

7:6

RESERVED

0,RO

Reserved

REEP

0,RW

Reload EEPROM. Driver needs to clear it up after the operation completes

WEP

0,RW

Write EEPROM Enable

EPOS

0,RW

EEPROM or PHY Operation Select

When reset, select EEPROM; when set, select PHY

ERPRR

0,RW

EEPROM Read or PHY Register Read Command. Driver needs to clear it up after

the operation completes.

ERPRW

0,RW

EEPROM Write or PHY Register Write Command. Driver needs to clear it up after

the operation completes.

ERRE

0,RO

EEPROM Access Status or PHY Access Status

When set, it indicates that the EEPROM or PHY access is in progress

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