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DM9000 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers |
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DM9000 Datasheet(HTML) 12 Page - List of Unclassifed Manufacturers |
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12 / 54 page  DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 12 Final Version: DM9000-DS-F02 June 26, 2002 MWRH Memory Data Write _ address Register High Byte FBH 00H TXPLL TX Packet Length Low Byte Register FCH XXH TXPLH TX Packet Length High Byte Register FDH XXH ISR Interrupt Status Register FEH 00H IMR Interrupt Mask Register FFH 00H Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value <Access Type>: RO = Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write 1 WO = Write only Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access. |
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