DM9000 datasheet(7/54 Pages) ETC

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DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F02

June 26, 2002

5. Pin Description

I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,

LI= reset Latch Input, #= asserted low

5.1 MII Interface

Pin No.

Pin Name

I/O

Description

LINK_I

External MII device link status

41,40,39,

RXD [3:0]

External MII Receive Data

4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode

CRS

I/O

External MII Carrier Sense

Active high to indicate the pressure of carrier, due to receive or transmit activities

in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.

COL

I/O

External MII Collision Detect. This pin is output in reverse MII interface.

RX_DV

External MII Receive Data Valid

RX_ER

External MII Receive Error

RX_CLK

External MII Receive Clock

TX_CLK

I/O

External MII Transmit Clock. This pin is output in reverse MII interface.

53,52,51,

TXD [3:0]

External MII Transmit Data

4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps

nibble mode

TXD [2:0] is also used as the strap pins of IO base address.

IO base = (strap pin value of TXD [2:0]) * 10H + 300H

TX_ EN

External MII Transmit Enable

MDIO

I/O

MII Serial Management Data

MDC

MII Serial Management Data Clock

This pin is also used as the strap pin of the polarity of the INT pin

When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin

is high active

Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally

5.2 Processor Interface

IOR#

Processor Read Command

This pin is low active at default, its polarity can be modified by EEPROM setting.

See the EEPROM content description for detail

IOW#

Processor Write Command

This pin is low active at default, its polarity can be modified by EEPROM setting.

See the EEPROM content description for detail

AEN

Address Enable

A low active signal used to select the DM9000.

IOWAIT

Processor Command Ready

When a command is issued before last command is completed, the IOWAIT will

be pulled low to indicate the current command is waited

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