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PCM5252 Datasheet(PDF) 48 Page - Texas Instruments

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Part # PCM5252
Description  Purepath Smart Amp PCM5252 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-
PDF  119 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCM5252 Datasheet(HTML) 48 Page - Texas Instruments

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PLL
Master Mode
BCK Integer
Divider
Master Mode
LRCK Integer
Divider
LRCK OUT
BCK OUT
NEW
AUDIO
SCK
NON AUDIO SCK
GPIOx
GPIOy
SCK
BCK
LRCK
PCM5252
SLASE63 – NOVEMBER 2014
www.ti.com
9.8.7 Clock Master from a Non-Audio Rate Master Clock
The classic example here is running 12MHz Master clock for a 48kHz sampling system. Given the clock tree for
the device (shown in Figure 63), a non-audio clock rate cannot be brought into the SCK to the PLL in master
mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another
GPIO pin.
Figure 65. Application diagram for using non-audio clock sources to generate audio clocks
The clock flow through the system is shown above. The newly generated SCK must be brought out of the device
on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.
NOTE
Pull up resistors should be used on BCK and LRCK in this mode to ensure the device
doesn't go into sleep mode.
A code example for configuring this mode is provided in SLAC622
48
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Product Folder Links: PCM5252



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