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PCM5252 Datasheet(PDF) 12 Page - Texas Instruments |
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PCM5252 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 119 page ![]() BCK tBCH tBCL tBCY t DS t DH tBL tLB DATA LRCK 0. 5 * DVDD 0. 5 * DVDD 0. 5 * DVDD (Input) (Input) (Input) DATA 0. 5 * DVDD ( Output) tDOD PCM5252 SLASE63 – NOVEMBER 2014 www.ti.com 8.8 Timing Requirements: PCM Audio Data MIN TYP MAX UNIT tBCY BCK Pulse Cycle Time 40 ns tBCL BCK Pulse Width LOW 16 ns tBCH BCK Pulse Width HIGH 16 ns tBL BCK Rising Edge to LRCK Edge 8 ns tBCK BCK frequency at DVDD = 3.3V 24.576 MHz tBCK(1.8V) BCK frequency at DVDD = 1.8V 12.288 MHz tLB LRCK Edge to BCK Rising Edge 8 ns tDS DATA Set Up Time 8 ns tDH DATA Hold Time 8 ns tDOD DATA delay time from BCK falling edge 15 ns Figure 5. PCM5252 Serial Audio Timing - Slave In software mode, tThe PCM5252 can act as an I2S master, generating BCK and LRCK as outputs from the SCK input. Table 3. I2S Master Mode Registers Register Function Page0, Register 9, D(0), D(4), and D(5) I2S Master mode select Register 32, D(6:0) BCK divider and LRCK divider Register 33, D(7:0) 12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: PCM5252 |
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