PCM5252 datasheet(49/119 Pages) TI1

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IDX6

IDX5

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IDX3

IDX2

IDX1

IDX0

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LSB

R/W

PCM5252

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SLASE63 – NOVEMBER 2014

9.9 Device Functional Modes

9.9.1 Choosing A Control Mode

SPI Mode is selected by connecting MODE1 to DVDD. SPI mode uses four signal lines and allows higher-speed

full-duplex communication between the host and the PCM5252.

I2C Mode is selected by connecting MODE1 to DGND and Mode2 to DVDD. I2C uses two signal lines for half-

duplex communication, and is widely used in a variety of devices.

Hardware Control Mode is selected by connecting both MODE1 and MODE2 pins to DGND. Hardware control is

useful in applications that do not require on-the-fly device-reconfiguration changes in operating features such as

gain or filter latency selection.

See Pin Assignments for a comparison of pin assignments for the 32-pin VQFN.

9.9.1.1 Software Control

9.9.1.1.1

SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface

and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.

The control interface includes MISO (pin 24), MOSI (pin 11), MC (pin 12), and MS (pin 18). MISO (Master In

Slave Out) is the serial data output, used to read back the values of the mode registers; MOSI (Master Out Slave

In) is the serial data input, used to program the mode registers.

MC is the serial bit clock, used to shift data in and out of the control port by falling edge of MC, and MS is the

mode control enable with LOW active, used to enable the internal mode register access. If feedback from the

device is not required, the MISO pin can be assigned to GPIO1 by register control.

9.9.1.1.1.1

All read/write operations for the serial control port use 16-bit data words. Figure 66 shows the control data word

format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read

operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or

address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written

to, or the data that was read from, the register specified by IDX[6:0].

Figure 66 and Figure 67 show the functional timing diagram to write or read through the serial control port. MS is

held at a logic-1 state until a register access. To start the register write or read cycle, set MS to logic 0. Sixteen

clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and read-back

data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register

appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched

into the indexed-mode control register during the write operation. To write or read subsequent data, MS is set to

logic 1 once (See tMHH in Figure 71).

Figure 66. Control Data Word Format; MDI

NOTE

B8 is used for selection of “Write” or “Read”. Setting = 0 indicates a “Write”, while = 1

indicates a ”Read”. Bits 15–9 are used for register address. Bits 7–0 are used for register

data. Multiple-byte write or read (up to 8 bytes) is supported while MS is kept low. The

address field becomes the initial address, automatically incrementing for each byte.

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