PCM5252 datasheet(98/119 Pages) TI1

98 / 119 page

PCM5252

SLASE63 – NOVEMBER 2014

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1: Error (clock auto set is not possible)

SCKval

SCK valid (Read Only)

This bit indicates whether the SCK is valid or not. The SCK ratio must be detectable to be valid. There is a

limitation with this flag, that is, when the low period of LRCK is less than or equal to 5 BCKs, this flag will be

asserted (SCK invalid reported).

0: SCK is valid

1: SCK is invalid

BCKval

BCK valid (Read Only)

This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-256FS

to be valid.

0: BCK is valid

1: BCK is invalid

fSval

fS valid (Read Only)

This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be

valid. There is a limitation with this flag, that is when this flag is asserted and Page 0 / Register 37 is set to

ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid

not reported anymore).

0: Sampling rate is valid

1: Sampling rate is invalid

Page 0 / Register 95

Dec

Hex

RSV

LTSH

RSV

CKMF

CSRF

CERF

Reset Value

RSV

Reserved

Reserved. Do not access.

LTSH

Latched Clock Halt (Read Only)

This bit indicates whether SCK halt has occurred. The bit is cleared when read.

0: SCK halt has not occurred

1: SCK halt has occurred since last read

CKMF

Clock Missing (Read Only)

This bit indicates whether the LRCK and BCK are missing (tied low).

0: LRCK and/or BCK is present

1: LRCK and BCK are missing

CSRF

Clock Resync Request (Read Only)

This bit indicates whether the clock resynchronization is in progress.

0: Not resynchronizing

1: Clock resynchronization is in progress

CERF

Clock Error (Read Only)

This bit indicates whether a clock error is being reported.

0: Clock is valid

1: Clock is invalid (Error)

Page 0 / Register 108

Dec

Hex

108

RSV

AMLM

AMRM

Reset Value

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