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PCM5252 Datasheet(PDF) 53 Page - Texas Instruments |
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PCM5252 Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 119 page  t BUF t S-HD t LOW t D-SU t D-HD t SCL-F t SCL-R t RS-HD t RS-SU t SP t P-SU SDA SCL t HI START Repeated START STOP t SDA-R t SDA-F PCM5252 www.ti.com SLASE63 – NOVEMBER 2014 Table 32. Write Operation - Basic I2C Framework Transmitter M M M S M S M S S M Data Type St slave address R/ ACK DATA ACK DATA ACK ACK Sp Table 33. Read Operation - Basic I2C Framework Transmitter M M M S S M S M M M Data Type St slave address R/ ACK DATA ACK DATA ACK NACK Sp M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition 9.9.1.1.2.4 Write Register A master can write to any PCM5252 registers using single or multiple accesses. The master sends a PCM5252 slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 34 shows the write operation. Table 34. Write Operation Transmitter M M M S M S M S M S S M reg write write Data Type St slave addr W ACK inc ACK ACK ACK ACK Sp addr data 1 data 2 M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge 9.9.1.1.2.5 Read Register A master can read the PCM5252 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM5252 slave address with a read bit after storing the register address. Then the PCM5252 transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 35 shows the read operation. Table 35. Read Operation Transmitter M M M S M S M M M S S M M M slave reg slave Data Type St W ACK inc ACK Sr R ACK data ACK NACK Sp addr addr addr M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge 9.9.1.1.2.6 Timing Characteristics Figure 74. Register Access Timing Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 53 Product Folder Links: PCM5252 |
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