PCM5252 datasheet(68/119 Pages) TI1

68 / 119 page

PCM5252

SLASE63 – NOVEMBER 2014

www.ti.com

13.3 PCM5252 Register Map

In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255

for next read or write command.

Table 38. Register Map Overview (continued)

Table 38. Register Map Overview

Auto mute time

Description

60 - 64

Digital volume

Number

Auto mute

Page 0

75 - 79

Reserved

Page select register

80 - 85

GPIOn output selection

Analog control register

86, 87

GPIO control

Standby, Powerdown requests

88, 89

Reserved

Mute

DSP overflow

PLL Lock Flag, PLL enable

91 - 94

Sample rate status

Reserved

95 - 107

Reserved

SPI MISO function select

108

Analog mute monitor

De-emphasis enable, SDOUT select

109 - 118

Reserved

GPIO enables

119

GPIO input

BCK, LRCLK configuration

120

Auto Mute flags

DSP GPIO Input

121

Reserved

Page 1

Master mode BCK, LRCLK reset

Output amplitude type

PLL clock source select

Analog gain control

14 - 19

Reserved

3, 4

Reserved

20 - 24

PLL dividers

Undervoltage protection

25, 26

Reserved

Analog mute control

DSP clock divider

Analog gain boost

DAC clock divider

8, 9

VCOM configuration

NCP clock divider

Page 44

OSR clock divider

Coefficient memory (CRAM) control

Reserved

Pages 44 - 52

Coefficient buffer - A (256 coeffs x 24 bits) : See

32, 33

Master mode dividers

Table 39

fS speed mode

Pages 62 - 70

Coefficient buffer - B (256 coeffs x 24 bits) : See

Table 40

35, 36

IDAC (number of DSP clock cycles available in

one audio frame)

Pages 152 -

Instruction buffer (1024 instruction x 25 bits),

186

I512 - I1023 are reserved.: See Table 41

Ignore various errors

Pages 187 -

Reserved

38,39

Reserved

252

40, 41

I2S configuration

Page 253

DAC data path

63, 64

Clock Flex Mode

DSP program selection

Pages 254 -

Reserved

Clock missing detection period

255

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