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PM6344 Datasheet(PDF) 170 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 170 Page - PMC-Sierra, Inc |
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170 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 157 RDEBE: The RDEBE bit enables debouncing of timeslot signaling bits. A logic 1 in this bit position enables signaling debouncing while a logic 0 disables it. When debouncing is selected, per-timeslot signaling transitions are ignored until two consecutive, equal values are sampled. A’,B’,C’ and D’: A’,B’,C’ and D’ are the per-timeslot signaling trunk conditioning bits. When trunk conditioning is enabled, these bits are used as signaling data, instead of the extracted timeslot signaling bits, and are output onto the BRSIG output. To enable the RINV[1:0], RTKCE and RDEBE bits, the PCCE bit in the SIGX Configuration Register must be set to logic 1. When these bits are enabled, bits RINV[1:0] and RDEBE are ORed with their primary input equivalents to generate the applied configuration signals. |
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