PM6344 datasheet(101/256 Pages) PMC

101 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

Unused

Bit 0

PSB[8]

This register contains the most significant bit of the 9-bit phase status word.

The PSB[8] bit toggles when the bit and timeslot count (from the Phase Status

Word LSB register) exceeds time slot 31, bit 7 or goes below time slot 0, bit 0.

The contents of the Phase Status Word registers are internally updated on each

receive line data frame pulse; a write to either Phase Status Word register

address must be performed to freeze the contents before this register and the

Phase Status Word (MSB) register can be read. The correct sequence for

reading the contents of the Phase Status Word are:

1. Write to either Phase Status Word register

2. Read Phase Status Word MSB

3. Read Phase Status Word LSB

This write-before-read is analogous to the latching of performance monitor

counter values in PMON, and is required to ensure that the phase status word

value remains valid during the µP read. It is important to read the MSB register

before the LSB register because, once the Phase Status Word (LSB) register has

been read, the phase status word counter is unfrozen and the contents may

change immediately.

PM6344 Datasheet(PDF) 101 Page - PMC-Sierra, Inc

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