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PM6344 Datasheet(PDF) 104 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 104 Page - PMC-Sierra, Inc |
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104 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 91 Register 011H, 091H, 111H, 191H: CDRC Interrupt Enable Bit Type Function Default Bit 7 R/W LCVE 0 Bit 6 R/W LOSE 0 Bit 5 R/W HDB3E 0 Bit 4 R/W Z4DE 0 Bit 3 Unused X Bit 2 Unused X Bit 1 Unused X Bit 0 Unused X The CDRC Interrupt Enable register allows the setting of specific events to cause an interrupt on the INTB pin. The Z4DE, HDB3E, LOSE, and LCVE bits of this register are interrupt enable bits used to select which of the indications (four consecutive zeros, HDB3 pattern, loss of signal, or line code violation) will generate an interrupt when their status changes. The occurrence of any of these events will generate an interrupt if there is a logic 1 in the corresponding bit position. When the EQUAD is reset, Z4DE, HDB3E, LOSE, and LCVE bits are set to logic 0, disabling any interrupt generation. |
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